Booting of blackfin BF527

Basic Booting process of Blackfin BF527 processor

1. Boot kernel resides on the on chip boot ROM
2. Boot stream is the specially formatted binary file of the project you have just built. Boot stream contains information such as where(SDRAM, internal memory etc) to load the data, what it contains(zero data or code) and the size
3. Once all the boot stream has been booted, the control is passed to user application code by jumping to the vector stored in the EVT1 register
4. Before passing the control to the application code, the boot kernel sets the registers to the default settings
5. During the boot process, boot kernel calls subroutine called Initcode. It helps in speeding up the boot process. Traditionally, Initcode is used to increase/optimize the core clock and system clock frequency, initialize SDRAM controller so that further booting occurs with out error
6. Software upgrade-ability is one application where the application code will be more than one depending on the need
7. Immediately after reset the control goes to 0xEF00 0000. It is the place where on chip boot rom resides
8. The boot kernel initializes the EVT1 register to 0xFFA0 0000. 
9. The following code snippet shows how the control is passed to lowest priority interrupt from highest priority interrupt 

_reset:

1. P0.L = LO(EVT15); /* Point to IVG15 in Event Vector Table */
   P0.H = HI(EVT15);
   P1.L = LO(_isr_IVG15); /* Point to start of IVG15 code */
   P1.H = HI(_isr_IVG15);
   [P0] = P1; /* Initialize interrupt vector EVT15 */
   P0.L = LO(IMASK); /* read-modify-write IMASK register */
   R0 = [P0]; /* to enable IVG15 interrupts */
   R1 = EVT_IVG15 (Z);
   R0 = R0 | R1; /* set IVG15 bit */
   [P0] = R0; /* write back to IMASK */
   RAISE 15; /* generate IVG15 interrupt request */
   /* IVG 15 is not served until reset handler returns */
   P0.L = LO(_usercode);
   P0.H = HI(_usercode);
   RETI = P0; /* RETI loaded with return address */
   RTI; /* Return from Reset Event */
   _reset.end:
   _usercode: /* Wait in user mode till IVG15 */
   JUMP _usercode; /* interrupt is serviced */
   _isr_IVG15: /* IVG15 vectors here due to EVT15 */

         ...
The _usercode will be main function normally.

The way adding software upgrade-ability to any user application in code is explained in detail in other post.

High speed digital design fundamentals - Probes

• A 3 inch ground wire used with a 10 pF probe induces a 2.8 ns of 10-90% rise time. 
• The response also rings when driven from a low impedance source
• Fattening ground wire hardly helps
• Radically shortening the ground loop improves ringing and reduces rise time
• To reduce the ground wire pickup loop area of the probe, ground the probe near the signal
• Keep the ground probe as short as possible

High speed Digital Design fundamentals - Power-Speed-Package

• Power dissipated in any device is not just related to Icc current rating given in the datasheet
• Quiescent power dissipation is the power dissipated while holding a logic state
• Active power dissipated in a device = (Cycle frequency) x (Excess energy used per cycle)
• Energy per cycle = (0.5 x C x Vcc x Vcc) x 2
• Therefore Power = F x C x Vcc x Vcc
• The cycle frequency is half of the operating frequency if the system is toggling between 1 and 0. It is 1/4th if the system toggles randomly
• Load of backplane capacitance is nearly 2 pF / inch
• The inputs pins of ICs still load the drivers in OFF condition. Hence extra care has to be taken when fanout is really huge, or power dissipation is a matter of importance
• Ground bounce is a problem which occurs due to inductance of individual leads
• Vgnd, ground bounce voltage = Lgnd x d/dt (Idischarge)
•  Everytime the capacitor discharges and charges, the inductance of the leads, develop voltage everytime the level toggles
• In DIP flipflops packages which have very fast drivers and if connected to huge capacitive loads see double clocking errors. The clock seen from external world looks fine. The Error is internal to the IC!
• Internal temperature of the logic device is also called junction temperature and is equal to sum of ambient temperature and a value proportional to internal power dissipation
• Tjunction = Tambient + Theta JA x P
• Theta JA is called thermal resistance from junction to ambient, of the package
• Most common method to divide thermal resistance is junction to case and case to ambient.
• Thermal resistance varies according to the die attachment method, package material, size etc
• The bigger the package smaller is the junction to case thermal resistance 
• Case to ambient thermal resistance can be reduced to certain extent using external heatsinks
• Standard manufactures state the thermal performance of device with heat sinks assuming airflow to be around 400 ft/min, typical PC fan is around 150 ft/min .
• 400 ft/min is a lot of air

High speed Digital Design fundamentals - Various Reactances in PCBs

Reactances

Digital Designers need to be aware of following four reactances sources that a signal sees on the board

• Normal capacitance
• Normal inductance
• Mutual Capacitance
• Mutual Inductance

Normal Capacitance

• The capacitance can be defined as the reluctance offered by the capacitor either to charge quickly or decay quickly.
• The initial current into the uncharged capacitor will be high, at short time scale, capacitor acts like short

Normal Inductance

• Inductance is everywhere, in all electric circuits
• The inductance can be defined as the reluctance offered by the inductor either to build up quickly or decay quickly.
• At short time scales, inductor acts as open circuit

Mutual capacitance

• Mutual capacitance is present wherever there are two or more circuits
• There will be interaction between two circuits. The level of interaction decays expoential with the increase in distance
• Unit: farads or amp-sec/volt
• Mutual capacitance coupling is like a parasitic capacitor connected between circuit 1 and circuit 2
• A mutual capacitance injects a current into circuit 2 which is proportional to the rate of change of voltage in circuit 1.
• Mutual capacitance is less harmful than mutual inductance
• Mutual capacitance of 8-10% may induce voltage levels of around 0.5 V

Mutual inductance

• Mutual inductance exists wherever there are two or more loop currents
• Coefficient of mutual inductance decreases as distance between two loop currents increases
•  Unit:henries or volt-sec/amp
• Quick changes in current in loop 1 induces large voltage in loop 2
• Similar to mutual  capacitance, the mutual inductance induces unwanted crosstalk between circuits
• Faraday's law states that the induced voltage Y(t) is proportional to the rate of change of flux in loop 1. Hence, a fraction of the total flux from loop 1 passes through loop 2.
• Overall, voltage induced in loop 2 is directly proportional to current in loop 1. Since magnetic field is vector quantity, the voltage induced reverses as direction of current reverses

High speed digital design fundamentals - Propagation delay in PCBs

Propagation delay

1. Propagation delay of signals in conducting wires increases as dielectric constant of medium surrounding the cable increases
2.  Both trace geometry and type of material used in PCB (Printed circuit board) defines the delay
3. The most used FR4 PCBs have the dielectric constant of 4.5
4. Delays on outer layer PCBs are always lower than that of inner layers since electric field shares outer air also and dielectric will be between 1 and 4.5
5. Popular propagation delay for signal propagating in a PCB is 160 ps/inch
6. Circuits with high rising/falling edges are not always lumped.
7. Length of rising edge L, in inches is given by ratio of Rise time (ps) to Delay (ps/inch). Circuits smaller than L/6 are lumped circuits
8. Treat PCBs with lengthier electrical features as distributed element

High speed digital design fundamentals - The beauty of decoupling capacitors in hardware design - Season 1

Quick Summary: Always choose more capacitor values spread over a considerable range. Let the Equivalent Series Resistor (ESR) of capacitor be nominal (Not high, never too low).  Place self resonating freq of caps closer.

Are capacitors with very low ESR figures beneficial?

No!. If ESR are very low, the impedance at minimum points decreases more (good!) and impedance at maximum points increases. The minimum and maximum points here refer to impedance curve. Hence, they are most of the time, not beneficial.

 What happens when ESR goes low?

When ESR goes low, troughs get deeper and the peaks get higher.

Is minimum impedance is equal to ESR?

No. It will be lower than that.

At resonance, what is the impedance through the Capacitor?

The impedance across the capacitor will be equal to R. Resonance occurs, by definition, when imaginary part of the impedance equation is zero.

If i parallel 100 capacitors, what is its effect on self resonance frequency?

Paralleling capacitors doesn't change the self resonating frequency, but it effectively increases the capacitance, reduces inductance and reduces ESR.

What is the phase angle when resonance occurs?

Theoretically Zero

What is the anti resonance frequency point?

When a pair of capacitors are connected in parallel, there will be point on impedance plot between self resonating frequencies of both capacitors. The impedance will be significantly high compared to neighbor points. It's the point where one of the capacitor's reactance will be inductive and increasing and other's reactance will be capacitive and decreasing.

What will be the impedance at anti resonance frequency?

Impedance is given by Z = R/2 + square(X)/2R; it is very important to note that the relationship is inversely related. Hence, the point - if ESR is very low, then impedance grows huge at anti resonance frequency. The second term in the RHS grows big if R is very small.

For some reason if capacitors with very less ESR values have to be used what is the better choice?

Option rather than choice is to use too many capacitors. Only then a relatively flat impedance response can be achieved. But, the BOM cost increases. What here needs to be appreciated here is more number of capacitors are required only because of low ESR. Hence while choosing capacitors always goes for nominal ESR. Low ESR has more bad and less good in stores for us.

Note: It is instructive to place self resonant frequencies closer, which is achieved using capacitor of wide range.

How to calculate value of ceramic capacitors required to bring down input ripple to a nominal value?

Following formula can be used:

                    Iout x DC x (1-DC) x 1000
Cmin =  ----------------------------------------- in  uF
                           Fsw x Vp(max)

Fsw - Switching frequency
Iout - Steady load current
Cmin - Minimum required ceramic input capacitance
Vp(max) - Maximum allowed peak to peak ripple voltage
DC - Duty cycle = Vout / (Vin x  n); n - Efficiency

Why are ceramic capacitors are placed next to tantalum capacitors at the input of switching regulators?

The extreme low ESR values of ceramic capacitors reduces ripple voltage significantly. Electrolytic capacitors are bulky and ESR figures are high and hence fails to reduce ripple effectively.
Also the large ESR values of tantalum capacitors leads to huge power dissipation because of higher ESR compared to ceramic.

How to calculate required value of bulk capacitor at input of switching regulator?

Following formula can be used:

                    1.21 x (Itr) x (Itr) x L
Cmin =  ------------------------------------- in  uF
                          delV x delV

Itr- Transient current
L - Value of filter(Inductor) in series at input voltage; if not populated a nominal value of 40 - 50 nH can be assumed which is parasitic inductance of trace and routing from host supply.
delV - Maximum allowable dip during peak transient step.

Comment on output capacitor selection for switching regulators

• External capacitors are required to achieve fast response to load transients
• Local decapacitors should be used to insure high frequency load regulation at point of load
• Low value of ceramic can be used abundantly
• Low ESR caps are recommended
• Impedance of the output capacitance affects the damping of the output filter

What is self resonant frequency of a capacitor?

For a given capacitor, self resonance frequency is the maximum frequency until which capacitor is usable. The Equivalent series Inductance (ESL) of capacitor dominates after this point.

The self resonance frequency of ceramic capacitor increases by a factor of 3.16 for every 10 times decrease in the capacitor value. 

Please share your opinion in the comments box below.

Source: White paper on Selection of Bypass caps for Decoupling by Douglas G Brooks